Emulators have been developed to assist circuit designers in designing and debugging highly complex integrated circuits. An emulator includes multiple reconfigurable components, such as field programmable gate arrays (FPGAs) that together can imitate the operations of a circuit under test (also referred to as a design under test (DUT)). By using an emulator to imitate the operations of a DUT, designers can verify that a DUT complies with various design requirements prior to a fabrication.
Analyzing the functionality or the operation of the DUT (e.g., power analysis) involves emulating the DUT and detecting certain states of multiple signals in the DUT tracked during the emulation. For example, numerous tracking components in addition to DUT are implemented to count a number of toggles for performing power analysis. For each signal that is tracked, an emulator typically has to implement numerous hardware resources (e.g., multiple registers or memories). Accordingly, an amount of resources for confirming the functionality or the operation of the DUT scales according to the number of signals. Hence, a great amount of hardware resources (e.g., processing cycles and/or memory) may have to be implemented by the emulator to accommodate additional hardware components to confirm the functionality or the operation of the DUT. In turn, this slows down the emulation process and limits the size of a DUT for which circuit analysis can be performed. In addition, a large amount of data (e.g., on the order of terabytes), which includes the detected states of the signals, is transferred to a host system for further processing. Transferring data to the host system requires a large amount of data bus or network bandwidth.
Therefore, analyzing the operations of the DUT in a conventional emulation environment is inefficient in terms of hardware and communication resources.